Samsung Exynos 2600 SoC Annotated, Showcases 3-tier CPU, AMD RDNA 4 iGPU

Die-shots of the Samsung Exynos 2600 application processor for smartphones, tablets, and ultraportable notebooks surfaced, and were annotated by Kurnal Salts. It showcases a massive logic complex with large amounts of on-die memory and compute muscle. Samsung buids the Exynos 2600 on Samsung SF2, the company's in-house 2 nm GAAFET foundry node, which offers comparable transistor densities and electrical specs to TSMC N2. It is a monolithic chip, with all logic components on die.

We begin our tour with the CPU. Samsung designed the Exynos 2600 with a 3-tiered heterogenous multicore design, and a 1X+3P+6E core configuration. Leading it is one C1-Ultra extreme core that ticks at up to 3.80 GHz, offers the highest IPC, and comes with 3 MB of dedicated L2 cache. Next to it are three C1-Pro performance cores, which run at up to 3.25 GHz, and handle most performance-heavy workloads. Each C1-Pro core has 1 MB of dedicated L2 cache. Trailing these are six other C1-Pro cores, which are purposed to serve as efficiency cores. Their clock speed only runs up to 2.75 GHz, and have a more aggressive power-management scheme. The "P-cores" and "E-cores" on this chip are functionally identical, and have the same transistor count, but are simply configured differently. The CPU complex is held together by 16 MB of shared L3 cache that all 10 cores have equal access to.